The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of the IC evolution, functional density (defined as the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. A scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has increased the complexity of processing and manufacturing ICs. For these advances to be realized, similar developments in IC manufacturing are needed.
As the semiconductor IC industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of three-dimensional (3D) devices, such as fin field effect transistors (FinFETs). Advantages of FinFET devices include reducing the short channel effect and increasing the current flow. There has been a desire to use a FinFET device with a high-k gate dielectric and a metal gate electrode to improve device performance as feature sizes continue to decrease.